1. Technical Field
The disclosure generally relates to a power-mode-aware clock tree and a synthesis method thereof.
2. Background
Integrated circuits (IC) with different power modes have been broadly adopted in order to reduce power consumption. FIG. 1 is a diagram of a clock tree (or a clock network) in a conventional IC. Referring to FIG. 1, the same IC (or chip) may be divided into different function modules, such as the micro-processor unit (MPU) 110 and the digital signal processor (DSP) 120. In a full speed power mode, both the MPU 110 and the DSP 120 operate under their maximum operating voltages (for example, 1.1V) under the control of a control circuit inside (or outside) the IC. In a power mode of a particular operation condition, the operating voltage VMPU of the MPU 110 remains at 1.1V, while the operating voltage VDSP of the DSP 120 is turned down (for example, to 1.0V) to reduce electricity consumption. In a power mode of another particular operation condition, the operating voltage VMPU of the MPU 110 remains at 1.1V, while the operating voltage VDSP of the DSP 120 is turned down to a even lower voltage (for example, 0.9V). In an idle mode, the operating voltage VMPU of the MPU 110 is turned down to 0.9V and the operating voltage VDSP of the DSP 120 is turned down to 0 V so that less electricity is consumed.
A clock tree can be automatically synthesized by using an electronic design automation (EDA) software at circuit synthesis. A clock tree is usually composed of a plurality of buffers (such as the buffers 101-107 illustrated in FIG. 1) for enhancing a system clock signal CLK and transmitting the enhanced system clock signal CLK to the next buffer or other devices. The system clock signal CLK can be sent to every element (not shown) in the IC through the clock tree. Ideally, the system clock signal CLK simultaneously reaches every element through the clock tree. Generally speaking, different factors (for example, the transmission paths and loads) may cause the system clock signal CLK to reach the elements in the IC at different time, and the difference between the time that the system clock signal CLK reaches different elements is called clock skew.
The EDA software can individually adjust the delay time of the buffers 101-107 regarding a particular operation condition, so as to optimize (minimize) the clock skew. For example, the EDA software can adjust the delay time of the buffers 101-107 regarding the full speed power mode so as to optimize the clock skew. However, because the operating voltage affects the performance of a clock buffer significantly, the time for the clock signal to reach every element changes obviously in different power mode. When the operating voltage VDSP of the DSP 120 is turned down from 1.1 V to 0.9 V, the clock delay of the DSP 120 increases, and the clock skew increases correspondingly. Thus, the clock tree illustrated in FIG. 1 cannot satisfy the clock skew restrictions in all the possible power modes.
Generally speaking, clock synchronization in a multi-power-mode design can be achieved through the asynchronous design, the adoption of an adjustable delay buffer (ADB), or the adoption of a delay locked loop (DLL). If the asynchronous design is adopted, a handshake protocol needs to be set up and accordingly the difficulty in designing and verifying the system is increased. Besides, any additional synchronization circuit needs to be disposed for synchronizing data. If the ADB or DLL is adopted, clock signals need to be sent back from a plurality of ends of the clock tree to perform phase comparison. Accordingly, additional ADB or DLL circuit design and disposition are required and the area cost is increased. Besides, the ADB or DLL requires an additional reference clock, and the selection of the reference clock may affect the synchronization effect.